The purpose of a via is to connect one conductor layer to another conductor layer in a printed circuit board or other substrate. The conductor layers are positioned between dielectric (insulating) layers.
One type of via is the plated through hole (PTH), in which a hole is drilled all the way through the circuit board. Following drilling through the circuit board the hole is plated with conductor. The conductor forms an electrical connection with each buried layer of conductor circuitry that it intersects. An example of a PTH is shown in FIG. 1A, which shows multiple layers of insulation 1 laminated together with layers of patterned conductor 2 between the insulation 1 layers. The detail of the patterned conductor 2 layers is not shown. To make connections between the patterned conductor 2 layers on different levels, a hole 3 is drilled through the laminated structure or formed by other suitable means. The hole 3 is plated with conductor 4 so that each layer of patterned conductor 2 may be electrically connected. If a connection is not desired between certain layers, the patterned conductor 2 must be relieved around the perimeter of the PTH. More than one PTH can be formed so that some conductor layers are connected by one PTH and other conductor layers are connected by another PTH. PTHs are simple to construct and are common in circuit boards. Capture pad 5 shows the typical geometry of the outermost conductive layer that a PTH intersects when no interconnection is required.
Another common structure is the buried via. A PTH can become a buried via if additional layers of insulating material are added to the structure on the top and bottom, so that the hole does not go through. Buried vias are also common, but are generally only found in more complex circuit boards consisting of multiple layers of dielectric and copper.
A cross section of a buried via is shown in FIG. 1B, where three layers of insulating material 11, 12, and 13, are laminated together. A buried via 14 is formed in the center of the middle insulating material layer 12. Middle insulating material 12 is also surrounded by patterned conductor layers 15 and 16 located on different levels in the multi-level structure. Although not shown, there could be patterned conductor layers below insulating material 11 and above insulating material 13. Buried via 14 is plated with conductor 17 to connect between patterned conductor layers 15 and 16. The buried via may or may not be filled with dielectric material as a result of subsequent lamination steps.
A third type of via is the "blind via", which is of another geometry and is generally found only in the most advanced circuit boards. While not necessarily complicated in terms of layers count, circuit boards can be characterized as advanced on the basis of having very fine features closely spaced together. For example, the state of the art for packaging integrated circuits is to mount them directly onto a very small, organic-based, printed circuit board as opposed to the traditional approach of mounting them onto a ceramic substrate. This approach is cheaper and better (organic materials used for making printed circuit boards have better dielectric properties than ceramic materials used for chip substrates). Blind vias are used in such high density printed circuit board applications because they save space and are suitable for making layer to layer connections thru even very thin insulating layers.
FIG. 1C shows a schematic cross sectional view of a blind via. There is shown a hole 21 plated with conductor 22 which terminates at patterned conducting layer 23. The plated hole 21 is surrounded by insulating material 24. Insulating material 24 is laminated to a partially completed printed circuit board consisting of patterned conductor 23 and dielectric layer 25. Additional conductor layers (not shown) and dielectric layers (not shown) can be connected to dielectric layer 25. Typically, conductor layers 27 and 26 would be patterned after lamination.
Contrasting a blind via with a PTH, a PTH would interfere with the circuitry which is represented in patterned conducting layer 26 shown in FIG. 1C. If blind via 21 was replaced by a PTH, the circuit layer 26 would have to be formed around the PTH. Furthermore, a capture pad would be required on layer 26, requiring additional space. Also, as a general rule, the deeper the hole, the larger its diameter must be for drilling, cleaning, and subsequent plating, therefore, taking up more space. Thus, a blind via saves space. The savings in space means higher density packaging which is electrically superior because all the circuit paths are shorter. Moreover, it can be less expensive to fabricate if greater integration is achieved.
There are three known methods to make blind vias. The first involves the use of a controlled depth drilling process. A conventional mechanical drill (widely used for hole making in printed circuit board fabrication) is used to make a partial depth hole. The problem with this approach is that for fine circuitry, the depth control is not precise enough. For example, with state of the art commercially available drill machines the depth control would be for example .+-.0.002 inches. This might be acceptable, but if the dielectric layers were 0.005 or less in thickness, these variations would be a significant fraction of the hole depth. In addition, a mechanical drill is not flat on the end; rather, it is pointed, thus making the bottom of the hole less uniform. In the case of very high frequency printed circuit boards, for example radio frequency, the geometric irregularity could cause electrical problems, acting as a tiny antenna when it protrudes as much as 0.004 inches further into a 0.005 inch dielectric layer than intended. Note that if the drill depth tolerance is .+-.0.002 inches, then the nominal drill depth must be set at 0.002 inches greater to ensure connection, resulting in a maximum of 0.004 inches protrusion.
A second process for making holes is laser ablation. This technique is growing in acceptance, but requires significant capital outlay, and is more suitable for some dielectric materials than others. A related process is the use of a mask next to the printed circuit board, the mask having holes corresponding to the desired hole locations, and the exposure to a plasma (ionized gas) that erodes the dielectric material. While there is prior art in this area, it is not widely practiced.
A third technique is referred to as surface laminar circuitry or SLC# (trademark of IBM Microelectronics). Here, a special dielectric material is used as the top layer of the circuit board. This layer is photo imageable, meaning that after it is applied it can be selectively polymerized by exposure to light and then developed such that portions remain only where the photo imageable layer was exposed to light. This technique can be used to form very small holes in the insulating layer that extend down to the next conductor layer.
Each of these three techniques are of interest in the industry, and reflect an industry wide effort to develop techniques to make micro vias. In each case the hole making process is different, but similar techniques are used to plate the hole with conductor after the hole is made to form the electrical interconnection.